学术报告：低功耗纳米晶体管
Low Power Nano-Transistors for Green-IT
报告人：Qing-Tai Zhao
Peter Grünberg Institute 9 (PGI 9), Forschungszentrum Juelich, Germany
邀请人：王卿璞教授
报告时间：2016年10月31日上午10:00
地点：中心校区理综楼301
报告摘要：
Abstract:
Our world is becoming “Smart” due to the fast development of smart electronic devices, like smartphones, smart cars, wearable devices and internet of things (IoT). Power consumption is the biggest challenge for these devices. Therefore, energy efficient transistors are highly desired. Due to the physical limit of MOSFETs, namely the minimum slope of 60 mV/dec, the applied voltage VDD is almost in saturation at around 0.7-0.8V. To reduce the power consumption, one solution is to improve the electrostatics by using FinFET or nanowire structure to minimize the short channel effects. However, the fabrication of well performing n- and p-type TFETs is still a great challenge. In this presentation, I will present Si nanowire MOSFETs and TFETs. Emphasis will be placed on strained silicon n-and p-type nanowire TFETs and first complementary inverters. Gate all around TFETs with nanowire diameter down to 10nm and SiGe/Si heretostructure TFETs employing line tunneling will be presented. Negative ferroelectric capacitance FETs will be also discussed.
报告人简介：
Biography:
Dr. Qing-Tai Zhao obtained his BS degree in 1987 and MS degree in 1990 both from Shandong University, and his PhD from Beijing University in 1993. Then he worked at Beijing University as an associate professor. In 1997 he was awarded as Humboldt Fellowship and started his research at Peter Grünberg Institute 9 (PGI 9), Forschungzentrum Juelich, where he is a senior research scientist and the leader of device group in PGI 9. He is the author and co-author of more than 230 scientific papers, and is the holder of ~10 EU and US patents (including pending patents). He is a guest professor at Shanghai Institute of Microsystem and Information Technology, the committee member of international MAM conference.
